A high-speed digital circuit such as, for example, a microprocessor includes a large number of registers that synchronize operation of the circuit. Ideally, these registers should be clocked at the same instance in time in order to maintain synchronization. In order to accomplish this, such circuits include a complex buffered clock tree that routes a clock signal from a clock source to the registers. Typically, the farther a register is from the clock source, the more clock insertion delay there is due to delays in the routing of the clock signal.
Conventional automated circuit design tools, such as synthesis place-and-route computer software, take clock insertion delay into account and produce clocking systems in which the clock latency through the clock tree is balanced to all registers. In these design tools, any differences in clock latency through the clock tree are undesirable and treated as noise. As a result, there is an inherent clock signal skew that occurs in digital circuits that include clock gaters. Clock gaters are used, for example, to inhibit operation of selected blocks of logic elements when the blocks are not needed, thereby conserving power and/or reducing heat generation. A secondary effect of clock gaters may be to buffer the clock signal (e.g., to restore strength to the clock signal so that it can drive multiple synchronizing registers).
The inherent clock signal skew that arises in digital circuits designed using conventional automated circuit design tools occurs because the enable pins of clock gaters are driven by synchronizing registers that receive the same clock signal as all the other registers in the circuit. But in order to perform their functions, clock gaters must be designed such that they are schematically or logically between the clock source and the registers they drive. The magnitude of this inherent clock signal skew is proportional, for example, to the routing delay between the clock input of a clock gater and the clock input of registers the clock gater drives. In a high-speed digital circuit, this inherent clock signal skew can be a critical timing path for the digital circuit and thereby make it impossible to automatically synthesize the digital circuit using conventional design tools.
What are needed are new design tools and techniques that overcome the deficiencies noted above and which are able to automatically synthesis digital circuits having clock gaters in which the clock insertion delay is large compared to the cycle time.